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Data Sheet No.PD60229
IR5001
UNIVERSAL ACTIVE ORING CONTROLLER
DESCRIPTION
The IR5001 is a universal high-speed controller and N-channel power MOSFET driver for Active ORing and reverse polarity protection applications. The output voltage of the IR5001 is determined based on the polarity of the voltage difference on its input terminals. In particular, if the current flow through an N-channel ORing FET is from source to drain, the output of the IR5001 will be pulled high to Vcc, thus turning the Active ORing FET on. If the current reverses direction and flows from drain to source (due to a short-circuit failure of the source, for example), the IC will quickly switch the Active ORing FET off. Typical turn-off delay for the IR5001 is only 130nS, which helps to minimize voltage sags on the redundant dc voltage. Both inputs to the IC (INN and INP) as well as Vline input contain integrated high voltage resistors and internal clamps. This makes the IR5001 suitable for applications at voltages up to 100V, and with a minimum number of external components.
FEATURES
Controller / driver IC in an SO-8 package for implementation of Active ORing / reverse polarity protection using N-channel Power MOSFETs Suitable for both input ORing (for carrier class telecom equipment) as well as output ORing for redundant DC-DC and AC-DC power supplies 130ns Typical Turn-Off delay time 3A Peak Turn-Off gate drive current Asymmetrical offset voltage of the internal high-speed comparator prevents potential oscillations at light load Ability to withstand continuous gate short conditions Integrated voltage clamps on both comparator inputs allow continuous application of up to 100V Option to be powered either directly from 36-75V universal telecom bus (100V max), or from an external bias supply and bias resistor Input/Output pins to determine the state of the Active ORing circuit and power system redundancy
APPLICATIONS
-48V/-24V Input Active ORing for carrier class communication equipment Reverse input polarity protection for DC-DC power supplies 24V/48V output active ORing for redundant AC-DC rectifiers Low output voltage (12V, 5V, 3.3V...) active ORing for redundant DC-DC and AC-DC power supplies Active ORing of multiple voltage regulators for redundant processor power
TYPICAL APPLICATION
+48V input
A B
PACKAGE / ORDERING INFORMATION
DC DC
IR5001
Vline Vcc Vout Gnd INN INP
FET Check Pulse FET A Status
FETch FETst
Top View
-48V input A
Vline 1
8 7 6 5
Vout Gnd INN INP
IR5001
Vline Vcc FETch
Fet B Status
Vcc 2 FETch 3 FETst 4
Vout Gnd INN INP
JA=128C/W
Ordering P/N IR5001S Package 8 - Pin SOIC
FETst
-48V input B
Figure 1 - Typical application of the IR5001 in - 48V input, carrier class telecommunications equipment.
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IR5001
ABSOLUTE MAXIMUM RATINGS
Vline Voltage Vcc Voltage Icc Current INN, INP Voltage FETch, FETst FETst Sink Current Junction Temperature Storage Temperature Range -5.0V to 100V (continuous) -0.5V to 15VDC 5mA -5.0V to 100V (continuous) -0.5V to 5.5V 10mA -40C to 125C -65C to 150C
CAUTION: 1. Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. 2. This device is ESD sensitive. Use of standard ESD handling precautions is required.
.
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vline = 36V to 100V; Vcc is decoupled with 0.1uF to Gnd, CL=10nF at Vout; INP is connected to Gnd. Typical values refer to TA=25C. Minimum and maximum limits apply to TA= 0C to 85C temperature range and are 100% production-tested at both temperature extremes. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature.
PARAMETERS Bias Section Vline Bias Current VCC output voltage UVLO Section UVLO ON Threshold Voltage SYMBOL Iline TEST CONDITION Vline=25V Vline=36V Vline=100V, Note 1 Vcc(out) MIN TYP MAX UNITS 0.14 0.2 1.2 0.3 0.5 1.7 0.5 0.75 2.2 V mA
Vline=25V 10.2 12.5 13.9 Vline=open, VINP=0; VINN= 0.3V 8.3 9.6 10.9 Vcc(ON) Vcc increased until Vout switches from LO to HI, Note 2 Vline=open, VINP=0, VINN=0.3V, Vcc is decreased until Vout switches from HI to LO 5.7 1.6 Vos VINP=0V and VINN Ramping up, VOUT changes from HI to LO, Fig.3 VINP=0,VINN ramping down, Figures 3 and 4 VINP=0V, VINN=36V VINN=0V, VINP=36V -7.9 7.2 2.3 -4.0 8.5 2.8 0
V
UVLO OFF Threshold Voltage UVLO Hysteresis Input Comparator Section Input Offset Voltage (VINPVINN) Input Hysteresis Voltage (INN) Input Bias Current (INP) Input Bias Current
Vcc(OFF)
V
mV 13 0.2 0.2 31 0.5 0.5 44 0.9 0.9 mA
Vhyst I(INN) I(INP)
2
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IR5001
PARAMETERS Output Section High Level Output Voltage Low Level Output Voltage Turn-On DelayTime Rise Time Turn-Off Delay Time Fall Time FETch and FETst FETch Sink Current FETch Output Delay Time FETch Threshold FETst Threshold Voltage FETst Low Level Output Voltage SYMBOL Vout HI Vout LO td(on) tr td(off) tf I(FETch) FETch_pd Vth(FETch) Vth(FETst) TEST CONDITION Vline=25V, IOH=50uA, V(INN)=-0.3V IOL=100mA, V(INN)=+0.3V Vout switching from LO to HI, Fig.5 Vout switching from HI to LO, Fig.5 FETch=5V Note 1 0.9 5k resistor from FETst to 5V logic bias. V(INP) = Gnd, V(INN) ramping down from 0 until FETst switches to Low. Isink=1mA, V(INN)=-0.5V MIN TYP MAX UNITS 9.5 12 14 V V us ms ns uA us V mV
0.1 0.1 5 27 45 0.1 0.7 5 110 130 170 10 26 39 -0.5 -1.1 0.8 1.2 -2 1.8 1.5
-525 -300 -200
VOL
0
50
100
mV
Note 1: Guaranteed by design but not tested in production. Note 2: Low Vcc output voltage corresponds to low UVLO voltage
PIN DESCRIPTIONS
PIN# 1 PIN SYMBOL Vline PIN DESCRIPTION IC power supply pin for 36V to 75V input communications systems. Minimum 25V has to be applied at this pin to bias the IC. Output pin of the internal shunt regulator, or input pin for biasing the IC via external resistor. This pin is internally regulated at 12.5V typical. A minimum 0.1uF capacitor must be connected from this pin to Gnd of IR5001. FET check input pin. Together with FET status output pin, the FETch pin can be used to determine the state of the Active ORing circuit and power system redundancy. FET status output pin. Together with FETch input pin, the FETst pin can be used to determine the state of the Active ORing circuit and power system redundancy. Positive input of internal comparator. This pin should connect to the source of N-channel Active ORing MOSFET. Negative input pin of internal comparator. This pin should connect to the drain of N-channel Active ORing MOSFET. Ground pin of the IR5001. Output pin for the IR5001. This pin is used to directly drive the gate of the Active Oring N-Channel MOSFET.
2
Vcc
3
FETch
4
FETst
5
INP
6 7 8
INN Gnd Vout
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IR5001
BLOCK DIAGRAM
VLINE Vcc
1 2
50K
12V Shunt Regulator 5V, VREF Generator
5V 1.25V 9V
UVLO
8
VOUT
7
Gnd
INP
5
70K
clamp
5V 3.5mV 28mV
12V Level Shifter
INN
6
70K
clamp
5V
4
FETst
0.3V 1.25V
FETch
3
2uA
Figure 2 - Simplified block diagram of the IR5001.
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IR5001
PARAMETER DEFINITION AND TIMING DIAGRAM
VOUT
VOUT VINN (VINP=Gnd)
-Vos
(0,0) VHYST VOS
VINP - VINN
Gnd VHYST
Figure 4 - Input Comparator Hysteresis Definition.
Figure 3 - Input Comparator Offset (Vos ) and Hysteresis Voltage (Vhyst) Definition.
10ns 90mV 50mV 0 VIN (VINP - VINN) td(on) VOH 90% 50% VOUT VOL 10% tr
Figure 5 - Dynamic Parameters.
10ns
VINP - VINN = 200mV
-50mV -90mV td(off)
tf
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IR5001
TYPICAL OPERATING CHARACTERISTICS
180 170 160 150 140 130 120 -40 -20 0 20 40 60 80 100 Temperature (C)
10.8 10.4 UVLO_upper (V) 10 9.6 9.2 8.8 8.4 -40 0 40 80 120 Temperature (C)
td(off) (ns)
Figure 6 - Turn Off Delay vs. Junction Temperature
Figure 7 - UVLO Upper Trip Point vs. Junction Temperature
5.7 5.6
28 26 Fall time (ns)
-40 -10 20 50 80 Temperature (C) 110 140
Vos value (mV)
5.5 5.4 5.3 5.2 5.1
24 22 20 18 16 -40 0 40 80 Temperature (C) 120
Figure 8 - Vos vs. Junction Temperature
Figure 9 - Fall Time vs. Junction Temperature
-280 -300 -320 -340 -360 -380
31 29 27 Hysteresis( mV) 25 23 21 19 17 15 -40 -10 20 50 80 Temperature (C) 110 140
FETst threshold (mV)
-40
-20
0
20 40 60 Temperature (C)
80
100
Figure 10 - INP, INN Input Hysteresis vs. Junction Temp.
Figure 11 - FETst Threshold Voltage vs. Junction Temp.
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IR5001
TYPICAL OPERATING CHARACTERISTICS
13 12.8 12.6 Vcc (V) 12.4 12.2 12 11.8 11.6 20 40 60 Vline (V) 80 100
Top: 25C 85C 125C Bottom: -40C
I Vline (mA)
1.75 1.5 1.25 1 0.75 0.5 0.25 0 20
Top: 125C 85C 25C Bottom: -40C
40
60 Vline (V)
80
100
Figure 12 - Vcc vs. Vline and Junction Temperature
Figure 13 - I(Vline) vs. Vline and Junction Temperature
1.4 1.2 1 Toff delay (nS) 20 40 60 INN (V) 80 100 I INN (mA) 0.8 0.6 0.4 0.2 0
121.0 120.5 120.0 119.5 119.0 118.5 118.0 117.5 117.0 20 40 60 Vline (V) 80 100
Figure 14 - Bias Current I(INN) vs. V(INN) at Vline=25V
Figure 15 - Turn Off Delay vs. Vline at Room Temperature
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IR5001
DETAILED PIN DESCRIPTION
Vline and Vcc Vline and Vcc are the input and output pins of the internal shunt regulator. The internal shunt regulator regulates the Vcc voltage at ~12V. The Vcc pin should always be by-passed with a ceramic capacitor to the Gnd pin. Both Vline and Vcc pins can be used for biasing the IR5001, as shown in Fig. 16. The Vline pin is designed to bias the IR5001 directly when the available bias voltage is above 25V and less than 100V (targeted at typical 36V - 75V telecom applications). This connection is shown in Fig 16.a. If the available Vbias voltage is lower than 25V, then the IC must be biased using Vcc pin and an external bias resistor as shown in Fig. 16.b. If the available bias voltage is above 100V, both Vline and Vcc pins can be used with an external bias resistor. For calculation of the proper bias resistor value, see example below.
IR5001 Vline Vcc Vbias
+
An example of Rbias calculation is given below. Vbias voltages used in the example are referenced to IR5001 Gnd: Vbias min = 12V Vbias max = 16V Rbias = (Vbias min - Vcc UVLOmax) / Icc min = = (12V - 10.9V) / 0.5mA = 2.2kOhm Next, using a minimum Vcc (10.2V), verify that Icc with the selected Rbias will be less than 5mA: Icc max = (Vbias max - Vcc min)/Rbias = = (16V - 10.2V) / 2.2kOhm = 2.6mA Since 2.6mA is below 5mA max Icc, the calculated Rbias (2.2kOhm) can be used in this design.
INP and INN Inputs INP and INN are the inputs of the internal highspeed comparator. Both pins have integrated onboard voltage clamps and high-voltage 70kOhm resistors. In a typical application, INP should be connected to the source of the N-FET and INN to the drain. To improve the noise immunity, the connections from INN and INP pins to the source and drain terminals of the N-FET should be as short as possible. The (INP - INN) voltage difference determines the state of the Vout pin of the IR5001. When the body diode of the Active ORing N-FET is forwardbiased and the current first starts flowing, the voltage difference INP - INN will quickly rise toward ~700mV (typical body diode forward voltage drop). As soon as this voltage exceeds Vhyst - Vos (27mV typical), the Vout of the IR5001 will be pulled high, turning the channel of the active ORing FET on. As the channel of the N-FET becomes fully enhanced, the (INP - INN) will reduce and stabilize at the value determined by the source-drain current, Isd, and Rds(on) of the N-FET: (INP - INN) steady state = Isd * RDS(on). If for some reason (due to a short-circuit failure of the source, for example), the current reverses direction and tries to flow from drain to source, the (INP - INN) will become negative; The IR5001 will then quickly pull its output low, switching the ORing FET off. For considerations regarding the selection of the Active ORing N-FET and RDS(on), see Applications Information Section. The offset voltage of the internal high-speed comparator is centered around negative 4mV, and is always less than 0mV. This asymmetrical offset
OUT Gnd INN INP
FETch FETst
a)
IR5001 Rbias Vline Vcc Vbias
+
OUT Gnd INN INP
FETch FETst
b)
Figue 16 - Biasing options for IR5001
When the Vcc pin is used for biasing the IR5001, the Vbias must always be higher than the maximum value of the Vcc UVLO threshold (10.9V). The Rbias resistor should always be connected between the Vbias voltage source and Vcc pin. The Rbias resistor is selected to provide adequate Icc current for the IC. The minimum required Icc to guarantee proper IC operation under all conditions is 0.5mA. The maximum Icc is specified at 5mA.
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IR5001
guarantees that once the ORing N-FET is conducting and Vout of the IR5001 is high (FET current flows from source to drain), the current must reverse the direction before the IR5001 will switch the FET off. The asymmetrical offset voltage prevents potential oscillations at light load that could otherwise occur if the offset voltage was centered around 0mV (as is the case in standard comparators). Vout Vout is the output pin of the IR5001, and connects directly to the gate of the external Active ORing NFET. The voltage level at the Vout pin is typically a diode drop lower than the Vcc voltage. functioning properly unless external circuitry is used. For example, the diode could be failed short, and the system would not be aware of it until the source fails and the whole system gets powered down due to lost redundancy (shorted diode failed to isolate the source failure). With the FETch pin it is possible to perform a periodic check of the status of the Active ORing circuit to assure that system redundancy is maintained. In the IR5001, the FETch pin is an input pin that can be used to turn off the output of the IR5001: logic high signal on FETch will pull the Vout pin low, and turn-off the channel of the Active ORing N-FET. This will force the current to flow through the body diode, resulting in VINP - VINN voltage increase from less than ~100mV, to ~700mV. This voltage increase will be reported at FETst pin, which will switch from logic high to logic low, and indicate that the Active ORing circuit is working properly. Failure of the FETst pin output to change from logic high to logic low would indicate that the Active ORing circuit may not be operating as designed, and the system may no longer have power redundancy. For details on how to use this feature consult IR5001 Evaluation Kit, P/N IRDC5001-LS48V. If t the FETch pin is not used, it should be tied to ground (for noise immunity purposes). If not used, FETst pin should be left open. Gnd In typical target applications, the ground pin (Gnd) of IR5001 is connected to the source of the Active ORing N-FET.
FETst and FETch FETch and FETst pins are diagnostic pins that can be used to determine the status of the Active ORing circuit. FETst is an open-drain output pin. When the voltage difference between VINP - VINN is less than 0.3V, the FETst pin will be logic high. This is normally the case when Active ORing is operating properly (VINP - VINN is less than ~100mV). If the Active ORing FET is not turned on while the IR5001 is properly biased, the output of the FETst pin will be logic low (only the body diode of the N-FET is conducting, and VINP - VINN is ~700mV). FETch pin. In traditional systems with diode ORing, it is not possible to determine if the diode is
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IR5001
APPLICATION INFORMATION
The IR5001 is designed for multiple active ORing and reverse polarity protection applications with minimal number of external components. Examples of typical circuit connections are shown below. Negative Rail ORing/Reverse Polarity Protection A typical connection of the IR5001 in negative rail Active ORing or reverse polarity protection is shown in Fig. 17. In this example, IR5001 is biased directly from the positive rail. However, any of the biasing schemes shown in Fig. 16 can be used. For input ORing in carrier-class communications boards, one IR5001 is used per feed. This is shown in Fig.1. An evaluation kit is available for typical system boards, with input voltages of negative 36V to negative 75V, and for power levels from 30W to about 300W. The p/n for the evaluation kit is IRDC5001-LS48V. This evaluation kit contains detailed design considerations and in-circuit performance data for the IR5001.
Vin +
Positive Rail ORing / Ground ORing in Communications Boards An example of a typical connection in positive rail ORing is shown in Fig. 18. Typical applications are inside redundant AC-DC and DC-DC power supplies, or on-board ORing. For positive rail ORing, an additional Vbias voltage above the positive rail is needed to bias the IR5001. An evaluation kit for high-current 12V positive rail ORing is available under p/n IRAC5001HS100A, demonstrating performance of the IR5001 at 100A output current. Considerations for the Selection of the Active ORing N-Channel MOSFET Active ORing FET losses are all conduction losses, and depend on the source-drain current and RDS(on) of the FET. The conduction loss could be virtually eliminated if a FET with very low RDS(on) was used. However, using arbitrarily low RDS(on) is not desirable for three reasons: 1. Turn off propagation delay. Higher RDS(on) will provide more voltage information to the internal comparator faster, and will result in faster FET turn off protection in case of short-circuit of the source (less voltage disturbance on the redundant bus. 2. Undetected reverse (drain to source) current flow. With the asymmetrical offset voltage, some small current can flow from the drain to source of the ORing FET and be undetected by the IR5001. The amount of undetected drain-source current depends on the RDS(on) of the selected MOSFET and its RDS(on). To keep the reverse (drain-source) current below 5 - 10% of the nominal source-drain state, the RDS(on) of the selected FET should produce 50mV to 100mV of the voltage drop during nominal operation. 3. Cost. With properly selected RDS(on), Active ORing using IR5001 can be very cost competitive with traditional ORing while providing huge power loss reduction. For example, a FET with 20mOhm RDS(on) results in 60mV voltage drop at 3A; associated power savings compared to the traditional diode ORing (assuming typical 0.6V forward voltage drop) is ten fold(0.18W vs. 1.8W)! Now assume that FET RDS(on) was 10mOhm. The power loss would be reduced by additional 90mW, which is negligible compared to the power loss reduction already achieved with 20mOhm FET. But to get this negligible saving, the cost of the Active ORing FET would increase significantly.
IR5001 Vline Rbias Vcc Vbias
+
OUT Gnd Load INN INP
FETch FETst
Vin -
Redundant Vin -
Figure. 17 Connection of INN, INP, and Gnd for negative rail Active ORing or reverse polarity protection.
Vout +
Redundant Vout +
IR5001 Rbias Vline Vcc Vbias
+
OUT Gnd INN INP Load
FETch FETst
Vout -
Figure. 18. Connection of INN,INP, and Gnd when the MOSFET is placed in the path of positive rail.
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IR5001
In a well - designed Active ORing circuit, the Rds(on) of the Active ORing FET should generate between 50mV to 100mV of (INP - INN) voltage during normal, steady state operation. (The normal operation refers to current flowing from the source to drain of the Active ORing FET, half of the full-load system current flowing through each OR-ed source, at nominal input voltage). Maximum power dissipation under worst-case conditions for the FET should be calculated and verified against the data sheet limits of the selected device. IR5001 Thermal considerations Maximum junction temperature of the IR5001 in an application should not exceed the maximum operating junction temperature, specified at 125C: Tj = Pdiss * Rtheta j-a + Tamb <= Tj (max), where Rtheta j-a is the thermal resistance from junction to ambient thermal resistance (specified at 128 C/W), Pdiss is IC power dissipation, and Tamb is operating ambient temperature. The maximum power dissipation can be estimated as follows:
Pdiss < (Tj max - Tamb max) / Rtheta j-a Since Tj max= 125 C, Tamb = 85 C, and Rtheta j-a = 128 C/W, the maximum power dissipation allowed is: Pdiss max = (125 - 85) / 128 = 0.3W With proper selection of Icc (as discussed in the Detailed Pin Description), the maximum power dissipation will never be exceeded (Max Icc * Max Vcc = 10mA * 13.9V = 0.14W). Layout Considerations INN and INP should be connected very close to the drain and source terminal of the Active ORing FET. PCB trace between the Vout pin and the gate of the N-FET should also be minimized. A minimum of 0.1uF decoupling capacitor must be connected from Vcc to Gnd of the IR5001and should be placed as close to the IR5001 as possible. Ground should be connected to the source of N-FET separately from the INP pin.
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IR5001
(S) SOIC Package 8-Pin Surface Mount, Narrow Body
H A B C
E
DETAIL-A PIN NO. 1 D 0.38 +/- 0.015 x 45 TF G
8-PIN SYMBOL A B C D E F G H I J K L T MAX MIN 4.98 4.80 1.27 BSC 0.53 REF 0.46 0.36 3.99 3.81 1.72 1.52 0.25 0.10 7 BSC 0.19 5.80 0 0.41 1.37 0.25 6.20 8 1.27 1.57
L DETAIL-A I J
K
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
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IR5001
PACKAGE SHIPMENT METHOD
PKG DESIG S PACKAGE DESCRIPTION SOIC, Narrow Body PIN COUNT 8 PARTS PER TUBE 95 PARTS PER REEL 2500 T&R Orientation Fig A
1
1
1
Feed Direction Figure A
This product has been designed and qualified for the industrial market
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 4/8/2005
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